1. Field of the Invention
This present invention relates to pipeline processing computer. In particular, it relates to an instruction rollback processor system, an instruction rollback method, and an instruction rollback program with low cost and high performance.
2. Description of the Related Art
In central processing units (CPU), since parallel processing speed increases as the number of stages of pipeline increases, an increased number of pipeline stages tends to be used. However, as the number of stages of the pipeline increases, restart time for the pipeline increases. This may lead to the shortcoming of the processing speed decreasing. When an out-of-order CPU cannot dispatch, when an instruction cannot be completely executed by an in-order CPU, or when a cache miss occurs during the execution of a load instruction, it is necessary to refill data and then re-issue instructions. Though there is a question whether instructions that may be re-issued can be terminated, those instructions are stored in an instruction window buffer in a conventional example. This operation is a part of rollback control. The load instruction and subsequent instructions have to be held and reserved for a predetermined time period, which is relevant to the depth of entry of the instructions.
With a conventional microprocessor system, re-issuing an instruction may be required due to an occurrence of data cache miss after that instruction has been issued. Conventionally, due to this, the instruction is kept within an instruction window buffer even after that instruction has been issued, and when it is determined that re-execution thereof is required, the instruction kept in the instruction window buffer is re-issued. This requires that the instruction should be stored in the instruction window buffer for a predetermined time period, creating a problem in which part of the instruction window buffer, which has a large cost per area, is occupied with entry and maintenance of the instruction.